1. Field of the Invention
The present invention relates to a DC-DC voltage boosting method and a power supply using the same. More particularly, the present invention relates to a DC-DC voltage boosting method and a power supply circuit of the charge pump type, which are incorporated in a voltage-boost power supply circuit for driving a liquid crystal device, or in a driver IC containing a power supply for driving a liquid crystal device.
2. Description of the Related Art
The following discussion provides the background for understanding the problems solved by the present invention. A liquid crystal device requires a high-voltage supply for driving liquid crystals, and the high-voltage power is generally obtained by DC-DC boosting. FIG. 13 shows a configuration of a typical power supply circuit incorporated in a driver IC for driving a liquid crystal device. This IC operates by receiving a power supply voltage VDD at the high potential side and a power supply voltage VSS at low potential side. Referring to FIG. 13, a voltage booster circuit 10 boosts the power supply voltage VDD at high potential side and outputs a boosted voltage VOUT. The boosted voltage VOUT is fed to a voltage regulator circuit 20, which outputs an operating voltage VLCD for operating the liquid crystal device. A voltage follower circuit 30 divides and buffers the operating voltage VLCD, and outputs voltages V1, V2, V3, and V4, in accordance with loads required for corresponding functions.
FIG. 14 is a circuit diagram showing an example of a configuration of the voltage booster circuit 10, and FIG. 15 shows an example of a configuration of the voltage regulator circuit 20. Referring to FIG. 14, a P-channel transistor Q1P and an N-channel transistor Q1N are connected in series between the supply voltage VDD at the high potential side and the power supply voltage VSS at the low potential side. In parallel to the P-channel transistor Q1P and the N-channel transistor Q1N, a P-channel transistor Q2P and an N-channel transistor Q2N are connected in series. P-channel transistors Q3, Q4, and Q5 are connected in series to the power supply voltage VDD at high potential side.
A capacitor C1 is connected between the source of the transistor Q3 and the drain of both the transistors Q1P and Q1N, and a capacitor C2 is connected between the source of the transistor Q4 and the drain of both the transistors Q2P and Q2N. The boosted voltage VOUT is obtained from the source of the transistor Q5.
FIG. 16 is a schematic representation showing wave formations of clock signals which are input to the voltage booster circuit shown in FIG. 14, in the case where the input voltage is tripled. A clock signal CL1P input to the gate of the transistor Q1P and a clock signal CL1N input to the gate of the transistor Q1N are the same. A clock signal CL2P input to the gate of the transistor Q2P and a clock signal CL2N input to the gate of the transistor Q2N are the opposition of the clock signal of CL1P and CL1N. The clock signals CL1P, CL1N, CL2P, and CL2N alternate between the power supply voltages VDD and VSS.
A clock signal CL3 input to the gate of the transistor Q3 and a clock signal CL5 input to the gate of the transistor Q5 are the opposition of the clock signal of CL1P and CLIN. A clock signal CL4 input to the gate of the transistor Q4 is the opposition of the clock signal of CL2P and CL2N. The clock signals CL3, CL4, and CL5 alternate between the boosted voltage VOUT and the power supply voltage VSS.
When the booster is used to double the input voltage, the clock signals CL2P and CL2N are fixed to the supply voltage VDD, while the clock signal CL5 is fixed to the supply voltage VSS.
When a driver IC for driving liquid crystals is of the chip-on-glass (COG) type so that the driver IC is mounted on a glass substrate, it is necessary to reduce electric terminals which connect a printed circuit substrate and a liquid crystal display device. Accordingly, the driver IC for driving liquid crystals is required to contain a charge pump capacitor for boosting a voltage.
From the viewpoint of reliability and costs, however, it is difficult to load the driver IC with large capacitors. An ability of a voltage-boost power supply to supply electric current depends on capacitance of capacitors and a frequency of switching. Therefore, switching with high frequency is required to obtain sufficient ability of the voltage-boost power supply to supply electric current.
Capacitors contained in ICs, however, always include stray capacitance. When the switching frequency increases, a reactive current due to charging and discharging of the stray capacitance also increases. FIG. 17 shows the stray capacitance.
Referring to FIG. 17(a), a lower electrode 93 of a capacitor is formed over a semiconductor substrate 91 via an insulator film 92, and an upper electrode 95 of the capacitor is formed above the lower electrode 93 via a dielectric material 94. Accordingly, the lower electrode 93 and the semiconductor substrate 91 carry stray capacitance CS between them.
Referring to FIG. 17(b), an N+ region 96 is formed in the semiconductor substrate 91 so as to be the lower electrode of the capacitor, and the upper electrode 95 is formed above the lower electrode 96 via the dielectric material 94. Accordingly, the lower electrode 96 and the semiconductor substrate 91 carry the stray capacitance CS between them.
Capacitors contained in an IC must be configured such that the stray capacitance is small, and the switching frequency must be adjusted to a necessary and sufficient value.
With regard to methods for adjusting the switching frequency, the methods disclosed in Japanese Unexamined Patent Application Publication Nos. 4-162560, 5-64429, and 7-160215 are known in the art. When a load current of the voltage-boost power supply is IOUT, however, a current which flows through the power supply voltage VDD is approximately the product of IOUT and a boosting ratio. Thus, to reduce power consumption, the boosting ratio must be set to a minimum value which satisfies the condition that the boosted voltage VOUT is larger than the operating voltage VLCD.
The boosted voltage VOUT varies with the output impedance and the load current IOUT of the voltage-boost power supply. The output impedance varies with the capacities of capacitors and the switching frequency. Since capacitors contained in an IC are small and the switching frequency is preferably low, the output impedance of the voltage-boost power supply tends to be large. The load current IOUT is determined primarily by a current charged and discharged by the liquid crystal panel, and the current charged and discharged by a liquid crystal panel varies with a display mode and display contents.
Since the boosted voltage VOUT varies significantly with the display mode and display contents, the boosting ratio must be adjusted to a minimum value required for the corresponding display mode and display contents. According to above-described Japanese Unexamined Patent Application Publications, however, only an adjustment of the switching frequency is provided and an adjustment of the boosting ratio is not considered. The adjustment of the boosting ratio may be achieved with software control using a microprocessor unit (MPU). In such a case, however, only an adjustment in accordance with the display mode is possible, and an adjustment in accordance with the display contents cannot be achieved.
Recently, the display capacity of liquid crystal panels has been increasing, and thus the power consumption of a driver IC for driving liquid crystals has tended to increase. An increase of power consumption, however, is not acceptable even when the display capacity is large, especially with portable devices. For such devices, the power consumption is decreased as much as possible by controlling the display mode.
In view of the above, an object of the present invention is to provide a DC-DC voltage boosting method and a booster circuit which are capable of cutting down the power consumption even when the display mode or the display content is changed, by detecting a margin of the boosted voltage.
Another object of the present invention is to provide a layout configuration which provides a low stray capacity and is suitable for an internal switching capacitor of an IC.
In order to solve the above-described problems, a DC-DC voltage boosting method according to a first aspect of the present invention provides the steps of (a) boosting an input voltage by using clock signals to generate a boosted voltage, (b) comparing the boosted voltage to at least one predetermined voltage, and (c) based on the comparison result in step (b), adjusting the frequency of the clock signals used in step (a) or fixing at least one of the clock signals which control switching components.
A power supply circuit according to a first aspect of the present invention includes a booster circuit to which an input voltage is supplied and which boosts the input voltage by using clock signals to generate a boosted voltage, a comparator circuit for comparing the boosted voltage generated by the booster circuit to at least one predetermined voltage, and a booster clock adjuster circuit which, based on the comparison result from the comparator circuit, adjusts the frequency of the clock signals used by the booster circuit or fixes at least one of the clock signals which control switching components.
A DC-DC voltage boosting method according to a second aspect of the present invention includes the steps of (a) boosting an input voltage by using clock signals to generate a boosted voltage, (b) generating a stabilized operating voltage by using the boosted voltage, (c) detecting a margin voltage between the boosted voltage and the operating voltage, and (d) based on the detected result in step (c), adjusting the frequency of the clock signals used in step (a) or fixing at least one of the clock signals which control switching components.
A power supply circuit according to a second aspect of the present invention includes a booster circuit to which an input voltage is supplied and which boosts the input voltage by using clock signals to generate a boosted voltage, a voltage regulator circuit which generates a stabilized operating voltage by using the boosted voltage generated by the booster circuit, a detector circuit for detecting a margin voltage between the boosted voltage generated by the booster circuit and the operating voltage generated by the voltage regulator circuit, and a booster clock adjuster circuit which, based on the detected result of the detector circuit, adjusts the frequency of the clock signals used by the booster circuit or fixes at least one of the clock signals which control switching components.
The boosting ratio of the input voltage may be changed by fixing at least one of the clock signals which control switching components.
The margin voltage may be compared to a first predetermined voltage and a second predetermined voltage. When the margin voltage is higher than the first predetermined voltage, the boosting ratio may be brought down by one level. When the margin voltage is lower than the first predetermined voltage and higher than the second predetermined voltage, the frequency of the clock signals may be brought down by one level. When the margin voltage is lower than the second predetermined voltage the frequency of the clock signals may be brought up by one level or the boosting ratio may be brought up by one level.
The margin voltage may be compared to first, second and third predetermined voltages. When the margin voltage is higher than the first predetermined voltage, the boosting ratio is brought down by one level. When the margin voltage is lower than the first predetermined voltage and higher than the second predetermined voltage, the frequency of the clock signals may be brought down by one level. When the margin voltage is lower than the second predetermined voltage and higher than the third predetermined voltage, the boosting ratio and the frequency of the clock signals may be maintained. When the margin voltage is lower than the third predetermined voltage, the frequency of the clock signals or the boosting ratio may be brought up by one level.
For the above-described power supply circuit, a booster clock generator circuit for generating and supplying to the booster circuit variable frequency clock signals may further be provided. The booster clock generation circuit may include a capacitor, a plurality of resistors, and a plurality of switch circuits which change the connections of the plurality of resistors corresponding to a plurality of control signals output from the booster clock adjuster circuit.
Furthermore, in the above-described power supply circuit, at least one capacitor whose the upper electrode and the lower electrode are impressed with signals in a first phase and at least one capacitor whose the upper electrode and the lower electrode are impressed with signals in a second phase which is the opposite phase of the first phase may be included in the booster circuit and may be arranged in M-by-N checkered manner (M and N are natural numbers).
The present invention having the above-described configuration is capable of reducing the power consumption even when the display mode or display content of the liquid crystal panel is changed, by detecting the margin of the boosted voltage and by adjusting the frequency of the clock signals or fixing at least one of the clock signals which control switching components.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.